A Single-Channel 14b 500 MS/s Pipelined-SAR ADC with Reference Ripple Mitigation Techniques and Adaptive-Biased Floating Inverter Amplifier
Author:
Affiliation:
1. University of Macau,State-Key Laboratory of Analog and Mixed-Signal VLSI/IME–DECE/FST,Macao,China
Funder
National Natural Science Foundation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9980472/9980536/09980749.pdf?arnumber=9980749
Reference7 articles.
1. 16.4 a calibration-free 71.7dB SNDR 100MS/s 0.7 mW weighted-averaging correlated level shifting pipelined SAR ADC with speed-enhancement scheme;hung;ISSCC,2020
2. 27.4 A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier
3. A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS;lin;VLSI,2016
4. A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS
5. A 10-Bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation
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1. A 12-bit 2.32GS/s pipelined/SAR hybrid ADC with a high-linearity input buffer;IEICE Electronics Express;2023-12-10
2. An 11bit 360MS/s Pipelined SAR ADC with Dynamic Negative-C Assisted Residue Amplifier;2023 IEEE Asian Solid-State Circuits Conference (A-SSCC);2023-11-05
3. A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier;IEEE Journal of Solid-State Circuits;2023-10
4. Three-Hop Underwater Wireless Communications: A Novel Relay Deployment Technique;IEEE Internet of Things Journal;2023-08-01
5. Collaborative Precoding Design for Adjacent Integrated Sensing and Communication Base Stations;IEEE Internet of Things Journal;2023
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