A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier-Reference-Cited by-同舟云学术

A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier

Published:2023-10 Issue:10 Volume:58 Page:2709-2721
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Jiang Wenning¹,Zhu Yan²^ORCID,Chen Chixiao¹^ORCID,Xu Hao³^ORCID,Liu Qi¹^ORCID,Liu Ming¹,Martins Rui P.²^ORCID,Chan Chi-Hang²^ORCID

Affiliation:

1. Frontier Institute of Chips and Systems, and the State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China

2. Institute of Microelectronics, Department of ECE/FST, State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China

3. State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China

Funder

National Natural Science Foundation of China

Macau FDCT

University of Macau

National Key Research and Development Program of China

Shanghai Rising-Star Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10262388/10175191.pdf?arnumber=10175191

Reference30 articles.

1. A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC

2. A 0.4-to-40 MS/s 75.7 dB-SNDR fully dynamic event-driven pipelined ADC with 3-stage cascoded floating inverter amplifier;tang;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2021

3. A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers

4. An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS

5. A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time

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