3D Stacking Using Bump-Less Process for Sub 10um Pitch Interconnects-Reference-Cited by-同舟云学术

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3D Stacking Using Bump-Less Process for Sub 10um Pitch Interconnects

Published:2016-05 Issue: Volume: Page:
ISSN:
Container-title:2016 IEEE 66th Electronic Components and Technology Conference (ECTC)
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Author:

Derakhshandeh Jaber,De Preter Inge,Gerets Carine,Hou Lin,Heylen Nancy,Beyne Eric,Beyer Gerald,Slabbekoorn John,Dubey Vikas,Jourdain Anne,Potoms Goedele,Inoue Fumihiro,Jamieson Geraldine,Vandersmissen Kevin,Suhard Samuel,Webers Tomas,Capuz Giovanni,Wang Teng,Rebibis Kenneth June,Miller Andy

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7542794/7545393/07545422.pdf?arnumber=7545422

Cited by 17 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Demonstration of Low Temperature Cu-Cu Hybrid Bonding using A Novel Thin Polymer;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

2. Bump-Less Interconnect with Room Temperature Pre-Bondable Adhesive and Solder for High Throughput Chip Stacking;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

3. 3D Integration via D2D Bump-Less Cu Bonding with Protruded and Recessed Topographies;ECS Journal of Solid State Science and Technology;2023-08-01

4. Micro-structure analysis of solder joint using room temperature Laser-Assisted Bonding (LAB) process;2023 IEEE 73rd Electronic Components and Technology Conference (ECTC);2023-05

5. Transient-Liquid-Phase Bonding of Granulated Cu–Sn Bumps With a 4-μm Fine Pitch;IEEE Transactions on Electron Devices;2023-02

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