1. 3D stacking using bump-less process for sub 10um pitch interconnects;Derakhshandeh,2016
2. Wafer level three-dimensional integration (3DI) using bumpless TSV interconnects for tera-scale generation;Ohba,2013
3. Volume 3: 3D Process Technology;Garrou,2014
4. Chip to wafer hybrid bonding with Cu interconnect: high volume manufacturing process compatibility study;Gao,2019
5. Recess effect study and process optimization of sub-10 μm pitch die-to-wafer hybrid bonding;Ren,2022