System-level clock jitter modeling for DDR systems-Reference-Cited by-同舟云学术

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System-level clock jitter modeling for DDR systems

Published:2013-05 Issue: Volume: Page:
ISSN:
Container-title:2013 IEEE 63rd Electronic Components and Technology Conference
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Author:

Shim Yujeong,Oh Dan,Khor Chuan Thim,Dhavale Bipin,Chandra Sunitha,Chow Daniel,Ding Weichi,Chand Kundan,Aflaki Aman,Sarmiento Mayra

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6573226/6575533/06575749.pdf?arnumber=6575749

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Modeling of a Voltage Regulator Module for Power Integrity: Power Supply Induced Jitter;IEEE Transactions on Signal and Power Integrity;2024

2. Signal and Power Integrity Design of Advanced Interface Bus (AIB) for FPGA Packages;2023 IEEE 32nd Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS);2023-10-15

3. On-Die Power-Rails Isolation Using Package Loop Inductance;2023 24th International Conference on Electronic Packaging Technology (ICEPT);2023-08-08

4. Prediction of Power Supply Induced Jitter With PDN Design Parameters;IEEE Transactions on Electromagnetic Compatibility;2022-12

5. Analysis of Pre-Driver and Last-Stage Power—Ground-Induced Jitter at Different PVT Corners;Sensors;2022-08-30

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