Signal and Power Integrity Design of Advanced Interface Bus (AIB) for FPGA Packages-Reference-Cited by-同舟云学术

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Signal and Power Integrity Design of Advanced Interface Bus (AIB) for FPGA Packages

Published:2023-10-15 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE 32nd Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)
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Author:

Wang Brian¹,Chen Guang²,Foo Loke Yip³,Jiang Xiaohong⁴

Affiliation:

1. Intel Corporation,Programmable Solutions Group,Folsom,USA

2. Intel Corporation,Programmable Solutions Group,Santa Clara,USA

3. Intel Corporation,Programmable Solutions Group,Penang,Malaysia

4. Intel Corporation,Programmable Solutions Group,San Jose,USA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10314857/10314859/10314935.pdf?arnumber=10314935

Reference3 articles.

1. In-depth analysis of power noise coupling between core and periphery power rails

2. System-level clock jitter modeling for DDR systems

3. What-if Jitter Analysis from Synthesized realistic PD Noises;wang;DesignCon Santa Clara,2016

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Signal, Power and Thermal Co-optimization Methodology for FPGA Advanced Package;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

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