Prediction of Power Supply Induced Jitter With PDN Design Parameters
Author:
Affiliation:
1. Zhejiang Lab, Hangzhou, China
2. Electromagnetic Compatibility Laboratory, Missouri University of Science and Technology, Rolla, MO, USA
Funder
National Science Foundation
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Atomic and Molecular Physics, and Optics
Link
https://ieeexplore.ieee.org/ielam/15/9985237/9880523-aam.pdf
Reference22 articles.
1. A Generalized Power Supply Induced Jitter Model Based on Power Supply Rejection Ratio Response
2. System-level clock jitter modeling for DDR systems
3. Chip-level power integrity methodology for high-speed serial links;shahramian,2018
4. Jitter-Aware Target Impedance
5. Supply Induced Jitter-aware Target Impedance Methodology To Solve Signoff Chip-pkg-pcb Co-design Flow
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Multiobjective Optimization for PSIJ Mitigation and Impedance Improvement Based on PCPS/DR-NSDE in Chiplet-Based 2.5-D Systems;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-08
2. Modeling of a Voltage Regulator Module for Power Integrity: Power Supply Induced Jitter;IEEE Transactions on Signal and Power Integrity;2024
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