Supply Induced Jitter-aware Target Impedance Methodology To Solve Signoff Chip-pkg-pcb Co-design Flow
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9027807/9038168/09038169.pdf?arnumber=9038169
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Analysis of the Effects of Power Partitioning in LPDDR4x Package for Enhanced EMC Design;2024 IEEE 28th Workshop on Signal and Power Integrity (SPI);2024-05-12
2. Prediction of Power Supply Induced Jitter With PDN Design Parameters;IEEE Transactions on Electromagnetic Compatibility;2022-12
3. Machine Learning-Based Verilog-A Modeling for Supply Induced Jitter Sensitivity of High-Speed Memory Interface: Two Layer PCB Case Study;2021 IEEE International Joint EMC/SI/PI and EMC Europe Symposium;2021-07-26
4. Supply Induced Jitter-Aware Method for SSO (Simultaneous Switching Noise) for Multiple IPs Integrated in Single Package Substrate;2020 IEEE Asia-Pacific Microwave Conference (APMC);2020-12-08
5. A Novel Laplace Transform Modeling for Supply Induced Jitter Sensitivity of SERDES Transmitter;2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM);2020-10-23
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