An Investigation on Border Traps in III–V MOSFETs With an In0.53Ga0.47As Channel-Reference-Cited by-同舟云学术

An Investigation on Border Traps in III–V MOSFETs With an In0.53Ga0.47As Channel

Published:2015-11 Issue:11 Volume:62 Page:3633-3639
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Ji Zhigang,Zhang Xiong,Franco Jacopo,Gao Rui,Duan Meng,Zhang Jian Fu,Zhang Wei Dong,Kaczer Ben,Alian Alireza,Linten Dimitri,Zhou Daisy,Collaert Nadine,De Gendt Stefan,Groeseneken Guido

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/7302109/07274328.pdf?arnumber=7274328

Cited by 38 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Demonstration of a lateral p-NiO/n-GaN JFET fabricated by selective-area regrowth;Semiconductor Science and Technology;2024-08-01

2. CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology;Nanomaterials;2024-05-09

3. Toward Reliability- and Variability-Aware Design-Technology Co-Optimization in Advanced Nodes: Defect Characterization, Industry-Friendly Modeling, and ML-Assisted Prediction;IEEE Transactions on Electron Devices;2024-01

4. A strong physical unclonable function with machine learning immunity for Internet of Things application;Science China Information Sciences;2023-12-18

5. On the Understanding of pMOS NBTI Degradation in Advance Nodes: Characterization, Modeling, and Exploration on the Physical Origin of Defects;IEEE Transactions on Electron Devices;2023-09