Toward Reliability- and Variability-Aware Design-Technology Co-Optimization in Advanced Nodes: Defect Characterization, Industry-Friendly Modeling, and ML-Assisted Prediction-Reference-Cited by-同舟云学术

Toward Reliability- and Variability-Aware Design-Technology Co-Optimization in Advanced Nodes: Defect Characterization, Industry-Friendly Modeling, and ML-Assisted Prediction

Published:2024-01 Issue:1 Volume:71 Page:138-150
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Ji Zhigang¹^ORCID,Xue Yongkang¹^ORCID,Ren Pengpeng¹^ORCID,Ye Jinfeng¹^ORCID,Li Yu²^ORCID,Wu Yishan¹,Wang Da¹^ORCID,Wang Shuying¹,Wu Junjie¹^ORCID,Wang Zirui²,Wen Yichen¹,Xia Shiyu¹,Zhang Lining²^ORCID,Zhang Jianfu³^ORCID,Liu Junhua²^ORCID,Luo Junwei⁴^ORCID,Deng Huixiong⁴,Wang Runsheng²^ORCID,Yang Lianfeng⁵,Huang Ru²

Affiliation:

1. National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Shanghai Jiaotong University, Shanghai, China

2. School of Integrated Circuits, Peking University, Beijing, China

3. Department of Electrical Engineering, Liverpool John Moores University, Liverpool, U.K

4. Center of Materials Science and Optoelectronics Engineering, UCAS, Beijing, China

5. Primarus Technologies, Shanghai, China

Funder

National Key Research and Development Program of China

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/10382412/10320313.pdf?arnumber=10320313

Reference53 articles.

1. Advanced Node DTCO in the EUV Era

2. Design-For-Reliability Flow in 7nm Products with Data Center and Automotive Applications

3. High performance, flexible CMOS circuits and sensors toward wearable healthcare applications

4. Impact of Self-Heating on the Statistical Variability in Bulk and SOI FinFETs

5. Performance and variability-aware SRAM design for gate-all-around nanosheets and benchmark with FinFETs at 3 nm technology node;Rzepa;IEDM Tech. Dig.,2022

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