The Understanding and Compact Modeling of Reliability in Modern Metal–Oxide–Semiconductor Field-Effect Transistors: From Single-Mode to Mixed-Mode Mechanisms
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Published:2024-01-12
Issue:1
Volume:15
Page:127
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ISSN:2072-666X
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Container-title:Micromachines
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language:en
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Short-container-title:Micromachines
Author:
Sun Zixuan1, Chen Sihao2ORCID, Zhang Lining2, Huang Ru1, Wang Runsheng1
Affiliation:
1. School of Integrated Circuits, Peking University, Beijing 100871, China 2. School of Electronic and Computer Engineering, Peking University Shenzhen Graduate School, Shenzhen 518055, China
Abstract
With the technological scaling of metal–oxide–semiconductor field-effect transistors (MOSFETs) and the scarcity of circuit design margins, the characteristics of device reliability have garnered widespread attention. Traditional single-mode reliability mechanisms and modeling are less sufficient to meet the demands of resilient circuit designs. Mixed-mode reliability mechanisms and modeling have become a focal point of future designs for reliability. This paper reviews the mechanisms and compact aging models of mixed-mode reliability. The mechanism and modeling method of mixed-mode reliability are discussed, including hot carrier degradation (HCD) with self-heating effect, mixed-mode aging of HCD and Bias Temperature Instability (BTI), off-state degradation (OSD), on-state time-dependent dielectric breakdown (TDDB), and metal electromigration (EM). The impact of alternating HCD-BTI stress conditions is also discussed. The results indicate that single-mode reliability analysis is insufficient for predicting the lifetime of advanced technology and circuits and provides guidance for future mixed-mode reliability analysis and modeling.
Reference116 articles.
1. Falcony, C., Aguilar-Frutis, M.A., and García-Hipólito, M. (2018). Spray Pyrolysis Technique; High-K Dielectric Films and Luminescent Materials: A Review. Micromachines, 9. 2. Wu, C., Lin, D., Keshavarzi, A., Huang, C., Chan, C., Tseng, C., Chen, C., Hsieh, C., Wong, K., and Cheng, M. (2010, January 6–8). High Performance 22/20nm FinFET CMOS Devices with Advanced High-K/Metal Gate Scheme. Proceedings of the 2010 International Electron Devices Meeting, San Francisco, CA, USA. 3. Smith, C., Adhikari, H., Lee, S., Coss, B., Parthasarathy, S., Young, C., Sassman, B., Cruz, M., Hobbs, C., and Majhi, P. (2009, January 7–9). Dual Channel FinFETs as a Single High-k/Metal Gate Solution beyond 22nm Node. Proceedings of the 2009 IEEE International Electron Devices Meeting (IEDM), Baltimore, MD, USA. 4. Yeh, C.-C., Chang, C.-S., Lin, H.-N., Tseng, W.-H., Lai, L.-S., Perng, T.-H., Lee, T.-L., Chang, C.-Y., Yao, L.-G., and Chen, C.-C. (2010, January 6–8). A Low Operating Power FinFET Transistor Module Featuring Scaled Gate Stack and Strain Engineering for 32/28 nm SoC Technology. Proceedings of the 2010 International Electron Devices Meeting, San Francisco, CA, USA. 5. Interactive Lattice and Process-Stress Responses in the Sub-7 Nm Germanium-Based Three-Dimensional Transistor Architecture of FinFET and Nanowire GAAFET;Lee;IEEE Trans. Electron Devices,2022
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