27.5 A multi-granularity FPGA with hierarchical interconnects for efficient and flexible mobile computing

Author:

Wang Cheng C.,Yuan Fang-Li,Yu Tsung-Han,Markovic Dejan

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A 16-nm 784-Core Digital Signal Processor Array, Assembled as a 2 × 2 Dielet With 10-μm Pitch Interdielet I/O for Runtime Multiprogram Reconfiguration;IEEE Journal of Solid-State Circuits;2023-01

2. Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design Flow;IEICE Transactions on Information and Systems;2021-08-01

3. Physical Design Considerations for Synthesizable Standard-Cell-Based FPGAs;Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies - HEART 2019;2019

4. Loop Parallelization Techniques for FPGA Accelerator Synthesis;Journal of Signal Processing Systems;2017-02-28

5. High-Density and High-Reliability Nonvolatile Field-Programmable Gate Array With Stacked 1D2R RRAM Array;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2016-01

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