Loop Parallelization Techniques for FPGA Accelerator Synthesis

Author:

Reiche Oliver,Özkan M. Akif,Hannig Frank,Teich Jürgen,Schmid Moritz

Publisher

Springer Science and Business Media LLC

Subject

Hardware and Architecture,Modelling and Simulation,Information Systems,Signal Processing,Theoretical Computer Science,Control and Systems Engineering

Reference38 articles.

1. Aditya, S., & Kathail, V. (2008). Algorithmic synthesis using PICO: An integrated framework for application engine synthesis and verification from high level C algorithms. In P. Coussy & A. Morawiec (Eds.), High-level synthesis: from algorithm to digital circuit (chap. 4, pp. 53–74). Springer. doi: 10.1007/978-1-4020-8588-8_4 .

2. Alias, C., Darte, A., & Plesco, A. (2013). Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA, Proceedings of the conference on design, automation and test in europe (DATE) (pp. 575–580).

3. Amdahl, G. (1967). Validity of the single processor approach to achieving large scale computing capabilities, Proceedings of the spring joint computer conference (AFIPS) (pp. 483–485).

4. Bailey, D. (2011). Design for embedded image processing on FPGAs. Wiley.

5. Bondhugula, U., Hartono, A., Ramanujam, J., & Sadayappan, P. (2008). A practical automatic polyhedral parallelizer and locality optimizer (Vol. 43, no. 6, pp. 101–113).

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