19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS

Author:

Shen Kuan-Yueh James,Farooq Syed Feruz Syed,Fan Yongping,Nguyen Khoa Minh,Wang Qi,Elshazly Amr,Kurd Nasser

Publisher

IEEE

Cited by 32 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Noise and Mismatch Improved Charge Pump for PLL in 28nm CMOS Technology;2024 International Conference on Integrated Circuits, Communication, and Computing Systems (ICIC3S);2024-06-08

2. A Near-Threshold Ring-Oscillator-Based ILCM with Edge-Selective Error Detector Achieving -64 dBc Reference-Spur and -239 dB FoM;ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC);2023-09-11

3. A 0.9 V wideband SPLL with an adaptive fast‐locking circuit achieving 24.68 µs settling time reduction;Electronics Letters;2023-07

4. Design and Analysis of the Self-Biased PLL with Adaptive Calibration for Minimum of the Charge Pump Current Mismatch;Electronics;2022-07-07

5. Comparative Analysis of Charge Pumps for PLL Applications;2022 IEEE International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE);2022-04-23

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