A Referenceless Digital CDR with a Half-Rate Jitter-Tolerant FD and a Multi-Bit Decimator

Author:

Kim JaekwonORCID,Ko Youngjun,Jin JahoonORCID,Choi Jaehyuk,Chun Jung-Hoon

Abstract

A referenceless digital clock and data recovery (D-CDR) circuit using a half-rate jitter-tolerant frequency detector (FD) and a multi-bit decimator is presented. For a referenceless configuration, we introduced a half-rate jitter-tolerant digital quadricorrelator frequency detector (JT-DQFD). Additionally, we proposed a multi-bit decimator circuit that losslessly down-samples up/down data from a phase detector to reduce the recovered clock jitter. The down-sampled multi-bit phase information is processed by a digital loop filter to adjust the phase of the recovered clock. Fabricated in a 28-nm CMOS technology, the test chip achieves a power efficiency of 1.3 pJ/bit at 10 Gb/s.

Funder

Samsung Electronics

Publisher

MDPI AG

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering

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