A 0.8-to-6.5 Gb/s Continuous-Rate Reference-Less Digital CDR With Half-Rate Common-Mode Clock-Embedded Signaling-Reference-Cited by-同舟云学术

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A 0.8-to-6.5 Gb/s Continuous-Rate Reference-Less Digital CDR With Half-Rate Common-Mode Clock-Embedded Signaling

Published:2016-04 Issue:4 Volume:63 Page:482-493
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Lee Kyongsu,Sim Jae-yoon

Funder

Basic Science Research Program

Ministry of Education

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/7454660/7434014.pdf?arnumber=7434014

Cited by 17 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 1–6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD;Microelectronics Journal;2024-09

2. A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4 Signaling Techniques;IEEE Journal of Solid-State Circuits;2024-08

3. A 1-6.5 Gbps Dual-Loop Cdr Design with Coarse-Fine Tuning Vco and Modified Dqfd;2024

4. A 0.8-6Gb/s wireline receiver based on the spectrum-balancing equalizer and semi-digital dual loop CDR;IEICE Electronics Express;2023-05-25

5. A Flexible 0.73–15.5 GHz Single LC VCO Clock Generator in 12 nm CMOS;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-11

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