A 0.9 V wideband SPLL with an adaptive fast‐locking circuit achieving 24.68 µs settling time reduction-Reference-Cited by-同舟云学术

A 0.9 V wideband SPLL with an adaptive fast‐locking circuit achieving 24.68 µs settling time reduction

Published:2023-07 Issue:13 Volume:59 Page:
ISSN:0013-5194
Container-title:Electronics Letters
language:en
Short-container-title:Electronics Letters

Author:

Wang Binghui¹²^ORCID,Shu Zhou³,Yang Haigang⁴⁵

Affiliation:

1. Aerospace Information Research Institute Chinese Academy of Sciences Beijing China

2. School of Electronic, Electrical and Communication Engineering University of Chinese Academy of Sciences Beijing China

3. School of Electrical and Electronic Engineering Nanyang Technological University Singapore Singapore

4. School of Microelectronics University of Chinese Academy of Sciences Beijing China

5. Shandong Industrial Institute of Integrated Circuits Technology Ltd. Jinan China

Abstract

AbstractA low‐power wideband self‐biased phase‐locked loop (SPLL) is proposed for multi‐protocol SerDes applications in this letter. With the proposed adaptive fast‐locking current circuit (AFLCC) and self‐biased charge pump (CP), the settling time is reduced significantly, and no extra power and jitter contribution. In addition, a start‐up module is adopted to reset the system to an optimal initial operating frequency quickly. The proposed 1‐3‐GHz SPLL, fabricated in TSMC 28‐nm CMOS process, occupies a compact 0.028 mm2 area. It achieves a roughly constant settling time of 5 μs over all frequencies and division ratios range. Only 0.96 mW is consumed at 1 GHz frequency.

Funder

National Natural Science Foundation of China

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

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