A 1.25-to-6.25 GHz −237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter-Reference-Cited by-同舟云学术

A 1.25-to-6.25 GHz −237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter

Published:2017 Issue:11 Volume:14 Page:20170422-20170422
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Zhang Zhao¹,Yang Jincheng¹,Liu Liyuan¹,Feng Peng¹,Liu Jian¹,Wu Nanjian¹

Affiliation:

1. State Key Laboratory of Super-Lattice and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, University of Chinese Academy of Sciences

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/14/11/14_14.20170422/_pdf

Reference13 articles.

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2. [2] S. D. Vamvakos, et al.: “A 2.488–11.2 Gb/s multi-protocol SerDes in 40 nm low-leakage CMOS for FPGA applications,” IEEE MWSCAS (2012) 5 (DOI: 10.1109/MWSCAS.2012.6291943).

3. [3] Z. Zhanget al.: “A 2.4–3.6-GHz wideband subharmonically injection-locked PLL with adaptive injection timing alignment technique,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25 (2017) 929 (DOI: 10.1109/TVLSI.2016.2619362).

4. [4] X. Kuang and N. Wu: “A fast-settling PLL frequency synthesizer with direct frequency presetting,” ISSCC Dig. Tech. Papers (2006) 741 (DOI: 10.1109/ISSCC.2006.1696113).

5. [5] A. Sai, et al.: “A digitally stabilized type-III PLL using ring VCO with 1.01 psrms integrated jitter in 65 nm CMOS,” ISSCC Dig. Tech. Papers (2012) 248 (DOI: 10.1109/ISSCC.2012.6176996).

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