Design Analysis of an Energy-Efficient Low-Power Dynamic Comparator Using NMOS Based Preamplifier-Reference-Cited by-同舟云学术

Design Analysis of an Energy-Efficient Low-Power Dynamic Comparator Using NMOS Based Preamplifier

Published:2023-07-06 Issue: Volume: Page:
ISSN:
Container-title:2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT)
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Author:

Saxena Abhinav¹,Yadav Anurag¹,Wairya Subodh¹

Affiliation:

1. Institute of Engineering and Technology,Department of Electronics and Communication Engineering,Lucknow,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10306338/10306339/10307939.pdf?arnumber=10307939

Reference23 articles.

1. Design and analysis of ultra high-speed low-power double tail dynamic comparator using charge sharing scheme

2. Analysis and design of low-voltage low-power high-speed double tail current dynamic latch comparator

3. Subodh Wairya Performance analysis of various fast and low power dynamic comparators, Intelligent Systems and Smart Infrastructure;khalid;© 2023 Taylor & Francis Group London 1st International Conference on Intelligent Systems and Smart Infrastructure jointly Organised by SIET Prayagraj IET Lucknow U P & Manipal University Jaipur Rajasthan on 21-22 May 2022,2022

4. Design and analysis of low-power high-speed shared charge reset technique based dynamic latch comparator

5. High-speed, low-power and low-offset fully differential double-tail dynamic comparator using charge sharing technique

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