Analysis and design of low-voltage low-power high-speed double tail current dynamic latch comparator

Author:

Savani VijayORCID,Devashrayee N. M.

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Reference28 articles.

1. Allen, P. E., & Holberg, D. R. (2002). CMOS analog circuit design. Oxford: Oxford University Press.

2. Baker, R. J., Li, H. W., & Boyce, D. E. (2005). CMOS: Circuit design, layout, and simulation. New York: IEEE press; Wiley-Interscience.

3. Carusone, T. C., Johns, D. A., & Martin, K. W. (2011). Analog integrated circuit design. New York: John Wiley & Sons.

4. Okaniwa, Y., Tamura, H., Kibune, M., Yamazaki, D., Cheung, T.-S., Ogawa, J., et al. (2005). A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. IEEE Journal of Solid-State Circuits, 40, 1680–1687. doi: 10.1109/JSSC.2005.852014 .

5. Maymandi-Nejad, M., & Sachdev, M. (2003). 1-bit quantizer with rail to rail input range for sub-1 V Sigma-Delta modulators. Electronics Letters, 39, 894–895. doi: 10.1049/el:20030588 .

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