Performance Analysis of Fast & Power Efficient Dynamic Comparator Topologies
Author:
Affiliation:
1. Institute of Engineering and Technology,Department of Electronics and Communication Engineering,Lucknow,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10532774/10532776/10533168.pdf?arnumber=10533168
Reference15 articles.
1. Design and analysis of low-power high-speed shared charge reset technique based dynamic latch comparator
2. A Low-Power 1-V Supply Dynamic Comparator
3. Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm CMOS
4. A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time
5. Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
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