High-speed, low-power and low-offset fully differential double-tail dynamic comparator using charge sharing technique
Author:
Publisher
Springer Science and Business Media LLC
Subject
Multidisciplinary
Link
https://link.springer.com/content/pdf/10.1007/s12046-020-01344-y.pdf
Reference15 articles.
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4. Khosrov D S 2010 A new offset cancelled latch comparator for high-speed, low-power ADCs. In: IEEE Asia Pacific Conference on Circuits and Systems, Kuala Lumpur, pp. 13–16
5. Kazeminia S and Mahdavi S 2016 A 800MS/s, 150 lV input referred offset single-stage latched comparator. In: MIXDES – 23rd international conference mixed design of integrated circuits and systems, pp. 119–123
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1. Design Analysis of an Energy-Efficient Low-Power Dynamic Comparator Using NMOS Based Preamplifier;2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT);2023-07-06
2. A complementary fully differential dynamic comparator with insensitive common-mode mismatch;IEICE Electronics Express;2022-08-25
3. A complementary fully differential dynamic comparator with insensitive common-mode mismatch;IEICE ELECTRON EXPR;2022
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