Realization of high A/R and fine pitch Cu pillars incorporating high speed electroplating with novel strip process-Reference-Cited by-同舟云学术

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Realization of high A/R and fine pitch Cu pillars incorporating high speed electroplating with novel strip process

Published:2022-05 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)
language:
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Author:

Park Se-Chul¹,Park Jong-Ho¹,Bae Seonghoon¹,Park Junyoung¹,Jung Taehwa¹,Yun Hyojin¹,Jeong Kwangok¹,Park Seok-Bong¹,Choi Ju-Il¹,Kang Un-Byoung¹,Kang Dongwoo¹

Affiliation:

1. Test & System Package (TSP) Samsung Electronics Co., Ltd,Cheonan-si,Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9816066/9816372/09816388.pdf?arnumber=9816388

Reference5 articles.

1. Multilayer resist technique for submicron optical lithography

2. Mechanisms involved in HBr and Ar cure plasma treatments applied to 193 nm photoresists

3. Plasma surface treatment on nylon fabrics by fluorocarbon compounds

4. Multilayer RDL Interposer for Heterogeneous Device and Module Integration

5. Heterogeneous integration roadmap;IEEE Electron Packag Soc,2019

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1. Design space exploration (DSE) for over-136GB/s IO bandwidth with LPDDR5X SDRAM packages on SOC package in 200mm³;2023 IEEE 73rd Electronic Components and Technology Conference (ECTC);2023-05

2. State-Of-The-Art of Advanced Packaging;Chiplet Design and Heterogeneous Integration Packaging;2023

3. Multiple System and Heterogeneous Integration with TSV-Less Interposers;Chiplet Design and Heterogeneous Integration Packaging;2023

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