A study on bonding pad structure and layout for Fine pitch hybrid bonding
Author:
Affiliation:
1. Test & System Package (TSP) Samsung Electronics Co., Ltd,Chungcheongnam-do,South Korea,31086
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9816066/9816372/09816514.pdf?arnumber=9816514
Reference5 articles.
1. Mechanisms for room temperature direct wafer bonding
2. Mechanism and Process Window Study for Die-to-Wafer (D2W) Hybrid Bonding
3. Modelling and characterization on wafer to wafer hybrid bonding technology for 3D IC packaging
4. Evaluation of hybrid bonding interface quality by contact resistivity measurement;joris;IEEE Transactions on Electron Devices,2019
5. Scalable, sub 2μm pitch, Cu/SiCN to Cu/SiCN hybrid wafer-to-wafer bonding technology
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