Wafer to Wafer Hybrid Bonding for DRAM Applications
Author:
Affiliation:
1. SK Hynix Semiconductor Co., LTD,R&D Center,Icheon,Republic of Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9816066/9816372/09816562.pdf?arnumber=9816562
Reference9 articles.
1. Excellent Reliability of XtackingTM Bonding Interface;ouyang;IEEE International Reliability Physics Symposium (IRPS),2021
2. Enabling Ultra-Thin Die to Wafer Hybrid Bonding for Future Heterogeneous Integrated Systems
3. A Stacked Embedded DRAM Array for LPDDR4/4X using Hybrid Bonding 3D Integration with 34GB/s/1Gb 0.88pJ/b Logic-to-Memory Interface
4. Novel stacked CMOS image sensor with advanced Cu2Cu hybrid bonding
5. Novel Cu/SiCN surface topography control for 1 μm pitch hybrid wafer-to-wafer bonding
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2. Quantifying the Electrical Impact of Bonding Misalignment for 0.5 μm Pitch Hybrid Bonding Structures;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28
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4. High-Throughput Characterization of Nanoscale Topography for Hybrid Bonding by Optical Interferometry;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28
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