A Stacked Embedded DRAM Array for LPDDR4/4X using Hybrid Bonding 3D Integration with 34GB/s/1Gb 0.88pJ/b Logic-to-Memory Interface-Reference-Cited by-同舟云学术

A Stacked Embedded DRAM Array for LPDDR4/4X using Hybrid Bonding 3D Integration with 34GB/s/1Gb 0.88pJ/b Logic-to-Memory Interface

Published:2020-12-12 Issue: Volume: Page:
ISSN:
Container-title:2020 IEEE International Electron Devices Meeting (IEDM)
language:
Short-container-title:

Author:

Fujun Bai¹,Xiping Jiang¹,Song Wang¹,Bing Yu¹,Jie Tan¹,Fengguo Zuo¹,Chunjuan Wang¹,Fan Wang¹,Xiaodong Long¹,Guoqing Yu¹,Ni Fu¹,Qiannan Li¹,Hua Li¹,Kexin Wang¹,Huifu Duan¹,Liang Bai¹,Xuerong Jia¹,Jin Li¹,Mei Li¹,Zhengwen Wang¹,Sheng Hu²,Jun Zhou²,Qiong Zhan²,Peng Sun²,Daohong Yang²,Kau Cheichan²,Yang David³,Ho Ching-Sung³,Hongbin Sun⁴,Hangbing Lv⁵,Ming Liu⁵,Yi Kang⁶,Qiwei Ren¹

Affiliation:

1. Xi'an UniIC Semiconductors Co., Ltd,Xi'an,China

2. Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.,Wuhan,China

3. Powerchip Semiconductor Manufacturing Corporation,Hsinchu,Taiwan

4. Xi'an Jiaotong University,Xi'an,China

5. Institute of Microelectronics of the Chinese Academy of Sciences,Beijing,China

6. University of Science and Technology of China,Hefei,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9371868/9371888/09372039.pdf?arnumber=9372039

Cited by 38 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Exploiting Similarity Opportunities of Emerging Vision AI Models on Hybrid Bonding Architecture;2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA);2024-06-29

2. Load Balanced PIM-Based Graph Processing;ACM Transactions on Design Automation of Electronic Systems;2024-06-21

3. Communication Minimized Model-Architecture Co-design for Efficient Convolution Acceleration;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12

4. Heterogeneous Oxide Semiconductor FETs Comprising Planar FET and Vertical Channel FETs Monolithically Stacked on Si CMOS, Enabling 1-Mbit 3D DRAM;2024 IEEE International Memory Workshop (IMW);2024-05-12

5. A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM;Micromachines;2024-04-23