Advanced Chip Last Process Integration for Fan Out WLP
Author:
Affiliation:
1. Test & System Package (TSP) Samsung Electronics Co., Ltd,Advanced Package Development Team,Chonan-Si,South Korea,31086
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9816066/9816372/09816684.pdf?arnumber=9816684
Reference10 articles.
1. Interconnect reliability prediction for wafer level packages (WLP) for temperature cycle and drop load conditions
2. Design and Reliability in Wafer Level Package;fan,2008
3. Photosensitive polymer reliability for fine pitch RDL applications
4. Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration
5. Low Cost Si-Less RDL Interposer Package for High Performance Computing Applications
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