Co-design and Signal-Power Integrity/EMI Co-analysis of a Switchable High-speed Inter-Chiplet Serial Link on an Active Interposer

Author:

Miao Min1,Duan Xiaolong1,Sun Liang1,Li Tao1,Zhu Shiliang1,Zhang Zhuanzhuan1,Li Jin1,Zhang Danya1,Wen Hao1,Liu Xuena1,Li Zhensong1

Affiliation:

1. Beijing Information Science and Technology University,A Member of Key Laboratory of the Ministry of Education for Optoelectronic Measurement Technology & Instrument,Academy of Smart IC and Network (ASICNet),Beijing,China

Funder

National Natural Science Foundation of China

Publisher

IEEE

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Signal and Power Integrity Co-Simulation of Chiplet-to-Chiplet Channel Based on Latency Insertion Method;2024 IEEE 28th Workshop on Signal and Power Integrity (SPI);2024-05-12

2. SPIRAL: Signal-Power Integrity Co-Analysis for High-Speed Inter-Chiplet Serial Links Validation;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

3. Chip Partition Heterogeneous Integration and Chip Split Heterogeneous Integration;Chiplet Design and Heterogeneous Integration Packaging;2023

4. Evaluation of Cost-Effective Flexible High-Speed Data Exchange Links for Heterogeneously Integrated Multi-Chip Modules and Boards;Journal of Nanoelectronics and Optoelectronics;2022-05-01

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