Co-design and Signal-Power Integrity/EMI Co-analysis of a Switchable High-speed Inter-Chiplet Serial Link on an Active Interposer
Author:
Affiliation:
1. Beijing Information Science and Technology University,A Member of Key Laboratory of the Ministry of Education for Optoelectronic Measurement Technology & Instrument,Academy of Smart IC and Network (ASICNet),Beijing,China
Funder
National Natural Science Foundation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9816066/9816372/09816691.pdf?arnumber=9816691
Reference2 articles.
1. Modeling and Design of Power Distribution Network for a Heterogeneous Integrated Active Interposer with Neuromorphic Computing Circuits
2. The Open Domain-Specific Architecture
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1. Signal and Power Integrity Co-Simulation of Chiplet-to-Chiplet Channel Based on Latency Insertion Method;2024 IEEE 28th Workshop on Signal and Power Integrity (SPI);2024-05-12
2. SPIRAL: Signal-Power Integrity Co-Analysis for High-Speed Inter-Chiplet Serial Links Validation;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22
3. Chip Partition Heterogeneous Integration and Chip Split Heterogeneous Integration;Chiplet Design and Heterogeneous Integration Packaging;2023
4. Evaluation of Cost-Effective Flexible High-Speed Data Exchange Links for Heterogeneously Integrated Multi-Chip Modules and Boards;Journal of Nanoelectronics and Optoelectronics;2022-05-01
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