Signal and Power Integrity Co-Simulation of Chiplet-to-Chiplet Channel Based on Latency Insertion Method
Author:
Affiliation:
1. University of Illinois at Urbana-Champaign,Department of Electrical and Computer Engineering,Urbana,IL,USA
Funder
U.S. Army Research Office
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10539129/10539187/10539220.pdf?arnumber=10539220
Reference11 articles.
1. Chiplet Heterogeneous Integration Technology—Status and Challenges
2. Signal and Power Integrity Design and Analysis for Bunch-of-Wires (BoW) Interface for Chiplet Integration on Advanced Packaging
3. Co-design and Signal-Power Integrity/EMI Co-analysis of a Switchable High-speed Inter-Chiplet Serial Link on an Active Interposer
4. On-chip PDN noise characterization and modeling;Sun
5. Latency insertion method (LIM) for the fast transient simulation of large networks
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