Signal and Power Integrity Design and Analysis for Bunch-of-Wires (BoW) Interface for Chiplet Integration on Advanced Packaging
Author:
Affiliation:
1. University of Illinois Urbana-Champaign,Urbana,USA
2. IBM Research,Yorktown Heights,USA
3. IBM Research,Albany,USA
Funder
IBM Research
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10195193/10195244/10195403.pdf?arnumber=10195403
Reference17 articles.
1. Chiplet Heterogeneous Integration
2. Universal Chiplet Interconnect Express (UCIe): An Open Industry Standard for Innovations With Chiplets at Package Level
3. Design and Development of High Density Fan-Out Wafer Level Package (HD-FOWLP) for Deep Neural Network (DNN) Chiplet Accelerators using Advanced Interface Bus (AIB)
4. Bunch of Wires: An Open Die-to-Die Interface
5. The Open Domain-Specific Architecture
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