Monolithic 3D integration of logic and memory: Carbon nanotube FETs, resistive RAM, and silicon FETs

Author:

Shulaker Max M.,Wu Tony F.,Pal Asish,Zhao Liang,Nishi Yoshio,Saraswat Krishna,Wong H.-S. Philip,Mitra Subhasish

Publisher

IEEE

Cited by 83 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Fault Diagnosis for Resistive Random Access Memory and Monolithic Inter-Tier Vias in Monolithic 3-D Integration;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-07

2. Comprehensive Physical Design Flow Incorporating 3-D Connections for Monolithic 3-D ICs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-07

3. A Compact Model of Carbon Nanotube Field-Effect Transistors for Various Sizes with Bipolar Characteristics;Electronics;2024-04-03

4. Monolithic 3D Integration using BEOL FeFET: Reliability, Thermal Effects, and DNN Accuracy;2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM);2024-03-03

5. Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

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