Fault Diagnosis for Resistive Random Access Memory and Monolithic Inter-Tier Vias in Monolithic 3-D Integration-Reference-Cited by-同舟云学术

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Fault Diagnosis for Resistive Random Access Memory and Monolithic Inter-Tier Vias in Monolithic 3-D Integration

Published:2024-07 Issue:7 Volume:32 Page:1336-1349
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Hung Shao-Chun¹^ORCID,Chaudhuri Arjun²,Banerjee Sanmitra³^ORCID,Chakrabarty Krishnendu³^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA

2. NVIDIA Corporation, Santa Clara, CA, USA

3. School of Electrical, Computer and Energy Engineering and the ASU Center for Semiconductor Microelectronics (ACME), Arizona State University, Tempe, AZ, USA

Funder

National Science Foundation

Center for Heterogeneous Integration of Micro Electronic Systems (CHIMES), one of the seven centers in JUMP 2

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

https://ieeexplore.ieee.org/ielam/92/10576042/10496590-aam.pdf

Reference33 articles.

1. Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration

2. A review of emerging non-volatile memory (NVM) technologies and applications

3. Challenges and opportunities for HfOX based resistive random access memory;Chen;IEDM Tech. Dig.,2011

4. Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design

5. High-Density 3D Monolithically Integrated Multiple 1T1R Multi-Level-Cell for Neural Networks

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