Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect-Reference-Cited by-同舟云学术

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Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect

Published:2024 Issue: Volume: Page:1-12
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Liu Hsiao-Hsuan¹^ORCID,Gilardi Carlo²^ORCID,Salahuddin Shairfe M.¹^ORCID,Pei Zhenlin³^ORCID,Schuddinck Pieter¹,Xiang Yang¹^ORCID,Weckx Pieter¹^ORCID,Hellings Geert¹^ORCID,Bardon Marie Garcia¹^ORCID,Ryckaert Julien¹,Pan Chenyun³^ORCID,Mitra Subhasish⁴^ORCID,Catthoor Francky¹^ORCID

Affiliation:

1. IMEC, Leuven, Belgium

2. Department of Electrical Engineering, Stanford University, Stanford, CA, USA

3. Department of Electrical Engineering, The University of Texas at Arlington, Arlington, TX, USA

4. Department of Electrical Engineering and the Department of Computer Science, Stanford University, Stanford, CA, USA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx8/8919/4358591/10561885.pdf?arnumber=10561885

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