Thermal resistance modeling of back-end interconnect and intrinsic FinFETs, and transient simulation of inverters with capacitive loading effects-Reference-Cited by-同舟云学术

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Thermal resistance modeling of back-end interconnect and intrinsic FinFETs, and transient simulation of inverters with capacitive loading effects

Published:2016-12 Issue: Volume: Page:
ISSN:
Container-title:2016 IEEE International Electron Devices Meeting (IEDM)
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Author:

Yan Jhih-Yang,Jan Sun-Rong,Peng Yu-Jiun,Lin H. H.,Wan W. K.,Huang Y.-H.,Hung Bigchoug,Chan K.-T.,Huang Michael,Yang M.-T.,Liu C. W.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7824662/7838021/07838550.pdf?arnumber=7838550

Cited by 21 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Study on the regulation factors and mechanism of self-heating effects in non-rectangular 14 nm bulk FinFET^*;Semiconductor Science and Technology;2024-08-14

2. EDA method to address interconnect reliability and reduce overdesign in custom analog designs;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14

3. The heat dissipation path of self-heating effects for the SOI MOSFET by considering the BOX layer and the TiN barrier layer;Journal of Physics D: Applied Physics;2024-02-01

4. Transient Self-Heating Effects on Mixed-Mode Hot Carrier and Bias Temperature Instability in FinFETs: Experiments and Modeling;IEEE Transactions on Electron Devices;2023-11

5. A Buried Thermal Rail (BTR) Technology to Improve Electrothermal Characteristics of Complementary Field-Effect Transistor (CFET);Micromachines;2023-09-07

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