Reliability of Wafer-Level Ultra-Thinning down to 3 µm using 20 nm-Node DRAMs-Reference-Cited by-同舟云学术

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Reliability of Wafer-Level Ultra-Thinning down to 3 µm using 20 nm-Node DRAMs

Published:2021-03 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE International Reliability Physics Symposium (IRPS)
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Author:

Chen Zhwen,Kim Youngsuk,Fukuda Tadashi,Sakui Koji,Ohba Takayuki,Kobayashi Tatsuji,Obara Takashi

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9405068/9405088/09405125.pdf?arnumber=9405125

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Novel Single and Co-Ion Implantation Induced Backside Etch Stop Structures for 3D Multilayer Stacked Package;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

2. Exploring circular water options for a water-stressed city: Water metabolism analysis for Paju City, South Korea;Sustainable Cities and Society;2023-02

3. Impact of Backside Defects on Device Characteristics of Ultra-Thin DRAMs with 3-5 μm Si Wafers for Bumpless Build Cube (BBCube) Application;2022 International Conference on Electronics Packaging (ICEP);2022-05-11

4. Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI);Electronics;2022-01-12

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