TSV Integration With Chip Level TSV-to-Pad Cu/SiO₂ Hybrid Bonding for DRAM Multiple Layer Stacking-Reference-Cited by-同舟云学术

TSV Integration With Chip Level TSV-to-Pad Cu/SiO₂ Hybrid Bonding for DRAM Multiple Layer Stacking

Published:2023-07 Issue:7 Volume:44 Page:1176-1179
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Hung Tzu-Heng¹,Lo James Yi-Jen²,Kuo Tzu-Ying³,Shih Shing-Yih²,Huang Sheng-Fu²,Lin Yen-Ling¹,Chiu Hsih-Yang²,Li Wei-Zhong²,Hu Han-Wen¹^ORCID,Chang Hsiang-Hung³,Shih Chiang-Lin²,Lin Jeff J. P.²,Chen Kuan-Neng¹^ORCID

Affiliation:

1. Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan

2. Technology Development Department, NANYA Technology Corporation, New Taipei, Taiwan

3. Electronics and Optoelectronics System Research Laboratories, Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/55/10168002/10136201.pdf?arnumber=10136201

Reference15 articles.

1. TSV residual Cu step height analysis by white light interferometry for 3D integration

2. Impact of post-plating anneal and through-silicon via dimensions on Cu pumping

3. Characteristics of Copper Nitride Nanolayer Used in 3D Cu Bonding Interconnects

4. Mechanisms for room temperature direct wafer bonding

5. Thermal degradation of DRAM retention time: Characterization and improving techniques

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