Author:
Noor Nur Qamarina Mohd,Yusof Yusrina,Saparon Azilah
Cited by
4 articles.
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1. Design and Analysis of Low-Transition Address Generator;Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering;2019
2. Test data compression for digital circuits using tetrad state skip scheme;Design Automation for Embedded Systems;2017-11-28
3. Low Power Memory Built in Self Test Address Generator Using Clock Controlled Linear Feedback Shift Registers;Journal of Electronic Testing;2014-02
4. Reducing Test Power for Embedded Memories;2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems;2011-10