Author:
Saravanan Sivasankaran,Hailu Mikias,Gouse G. Mohammed,Lavanya Mohan,Vijaysai R.
Publisher
Springer International Publishing
Reference22 articles.
1. Abuissa, A.S., Quigleyr, S.F.: LTPRPG: power minimization technique for test-per-scan BIST. In: International Conference on Design and Technology of Integrated Systems in Nanoscale Era, pp. 1–5 (2008)
2. Marinissen, E.J., Prince, B., Keitel-Schulz, D., Zorian, Y.: Challenges in embedded memory design and test. In: Proceedings of Design Automation Test in Europe, vol. 52, pp. 722–727 (2005)
3. Noor, N.Q., Yusof, Y., Sparon, A.: Low area FSM-based memory BIST for synchronous SRAM. In: Proceedings of the International Colloquium of Signal Processing and Its Application, pp. 409–412 (2009)
4. Van de Goor A.D.J., Kukner, H., Hamdioui, S.: Optimizing memory BIST address generator implementations. In: 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, pp. 1–6 (2011)
5. Wang, L.T., Stroud, C.E., Toubam, N.A.: System On Chip Test Architectures, pp. 308–339. Morgan Kaufmann, Los Altos (2008)
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