Generation of address sequences with specified switching activity and address repeatability

Abstract

Objectives. The problem of developing a methodology for generating address sequences with a given switching activity and repeatability of addresses widely used in testing modern computing systems is being solved. The relevance of this problem lies in the fact that the main characteristic of the difference and their effectiveness for address sequences is the switching activity of both individual address bits and their sequences.Methods. Presented results are based on a universal method for generating quasi-random Sobol sequences, which are effectively used to generate targeted test sequences. As an initial mathematical model, a modification of the indicated generation method proposed by Antonov and Saleev is used. The main idea of proposed approach is based on the use of rectangular (m + k) × m generating matrices V of arbitrary rank r to generate address sequences.Results. The main properties of sequences generated in accordance with the new mathematical model are determined. A number of statements are given that substantiate the requirements for generator matrices to ensure the maximum period of generated sequences and the multiplicity of repetition of used addresses. The problem of synthesizing the sequences with given values of switching activity F(A) and F(ai) is solved. It is shown that in order to find a generating matrix for generating such sequences, it is necessary to solve the problem of decomposing an integer into terms. This decomposition represents the value of switching activity in the (m + k)-ary mixed number system, in which the weights of the digits are represented as powers of two from 20 to 2m+k-1, and the values of the digits w(vi) lie in the range from 0 to m+k-1. On the basis of proposed restrictions, the notion of an integer decomposition diagram similar to the Young diagram is introduced, and the operation of its modification is defined.Conclusion. The proposed mathematical model expands the possibilities of generating test address sequences with the required values of switching activity of both test sets and their individual bits. The use of generating matrices of non-maximal rank makes it possible to formalize the method of generating address sequences with even repetition of addresses.