Low Power Memory Built in Self Test Address Generator Using Clock Controlled Linear Feedback Shift Registers
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
http://link.springer.com/content/pdf/10.1007/s10836-014-5432-1.pdf
Reference20 articles.
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2. Abu-Rahma MH, Anis M, Yoon SS (2010) Reducing SRAM power using fine-grained wordline pulse width control. IEEE Trans On Very Large Scale Integr (VLSI) Syst 18(3):356–364
3. Awad AN, Abu-Issa AS (2007) Low power address generator for memory built-in self test. Res Bull Jordan ACM III(II):52–56
4. Hsu C-L, Chen T-H (2009) Built-in self-test design for fault detection and fault diagnosis in SRAM-based FPGA. IEEE Trans Instrum Meas 58(7):2196–2208
5. Kumar TN, Lombardi F (2013) A novel heuristic method for application-dependent testing of a SRAM-based FPGA interconnect. IEEE Trans Comput 62(1):163–172
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