PLL/DLL system noise analysis for low jitter clock synthesizer design-Reference-Cited by-同舟云学术

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PLL/DLL system noise analysis for low jitter clock synthesizer design

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Container-title:Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94
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Author:

Beomsup Kim ,Weigandt T.C.,Gray P.R.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx2/3224/9172/00409189.pdf?arnumber=409189

Cited by 18 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Analysis and design of a low jitter delay‐locked loop using lock state detector;International Journal of Circuit Theory and Applications;2021-03-15

2. A 2–4 GHz fast-locking frequency multiplying delay-locked loop;IEICE Electronics Express;2017

3. A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques;IEEE Journal of Solid-State Circuits;2016-04

4. Design and Modeling of PLL based 1GHz Frequency Synthesizer using 0.35Μm SiGeBiCMOS Process;Proceedings of the International Conference on Advances in Information Communication Technology & Computing - AICTC '16;2016

5. An 8 GHz First-Order Frequency Synthesizer for Low-Power On-Chip Clock Generation;IEEE Journal of Solid-State Circuits;2015-08

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