A 2–4 GHz fast-locking frequency multiplying delay-locked loop-Reference-Cited by-同舟云学术

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A 2–4 GHz fast-locking frequency multiplying delay-locked loop

Published:2017 Issue:2 Volume:14 Page:20161056-20161056
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Kim Jongsun¹,Bae B-H¹

Affiliation:

1. Electronic and Electrical Engineering, Hongik University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/14/2/14_13.20161056/_pdf

Reference13 articles.

1. [1] B. Kim, et al.: “PLL/DLL system noise analysis for low jitter clock synthesizer design,” Proc. Int. Symp. Circuits and Systems (1994) 31 (DOI: 10.1109/ISCAS.1994.409189).

2. [2] K. J. Nowkaet al.: “A 32-bit powerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling,” IEEE J. Solid-State Circuits 37 (2002) 1441 (DOI: 10.1109/JSSC.2002.803941).

3. [3] C. Veneruset al.: “A TDC-free mostly-digital FDC-PLL frequency synthesizer with a 2.8–3.5 GHz DCO,” IEEE J. Solid-State Circuits 50 (2015) 450 (DOI: 10.1109/JSSC.2014.2361523).

4. [4] B. Catli, et al.: “A sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications,” IEEE Custom Integrated Circuits Conference (2013) 1 (DOI: 10.1109/CICC.2013.6658471).

5. [5] R. Farjad-Radet al.: “A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips,” IEEE J. Solid-State Circuits 37 (2002) 1804 (DOI: 10.1109/JSSC.2002.804340).

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