Pre-Layout Parasitic-Aware Design Optimizing for RF Circuits Using Graph Neural Network

Abstract

The performance of analog and RF circuits is widely affected by the interconnection parasitic in the circuit. With the progress of technology, interconnection parasitics plays a larger role in performance deterioration. To solve this problem, designers must repeat layout design and validation process. In order to achieve an upgrade in the design efficiency, in this paper, a Graph Neural Network (GNN)-based pre-layout parasitic parameter prediction method is proposed and applied to the design optimization of a 28 nm PLL. With the new method adopted, the frequency band overlap rate of the VCO is improved by 2.3 percents for an equal design effort. Similarly, the optimized CP is superior to the traditional method with a 15 ps mismatch time. These improvements are achieved under the premise of greatly saving the optimization iteration and verification costs.