Author:
Shook Brett,Bhansali Prateek,Kashyap Chandramouli,Amin Chirayu,Joshi Siddhartha
Cited by
25 articles.
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1. Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12
2. Edge-weighted Graph Neural Networks for Post-placement Interconnect Capacitance Estimation of Analog Circuits;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
3. Evaluation Trends and Development In Integrated Circuit Parasitic Extraction;2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS);2024-02-24
4. Post-Layout Parasitic Capacitance Prediction Methodology Using Bayesian Optimization;2024 International Conference on Electronics, Information, and Communication (ICEIC);2024-01-28
5. Toward End-to-End Analog Design Automation with ML and Data-Driven Approaches (Invited Paper);2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22