Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs

Author:

Shen Shan1ORCID,Yang Dingcheng2ORCID,Xie Yuyang2ORCID,Pei Chunyan2ORCID,Yu Bei3ORCID,Yu Wenjian2ORCID

Affiliation:

1. Department of Computer Science, Tsinghua University, China

2. Tsinghua University, China

3. The Chinese University of Hong Kong, China

Funder

the National Science and Technology Major Project

the National Natural Science Foundation of China

Publisher

ACM

Reference24 articles.

1. ARM. 2023. Artisan Embedded Memory IP. https://www.arm.com/en/products/silicon-ip-physical/embedded-memory

2. A 0.2 V 32-Kb 10T SRAM with 41 nW standby power for IoT applications;Chien Yung-Chen;IEEE Trans. Circuits Syst.,2018

3. Weibing Gong, Wenjian Yu, Yongqiang Lü, Qiming Tang, Qiang Zhou, and Yici Cai. 2010. A parasitic extraction method of VLSI interconnects for pre-route timing analysis. In Proc. Int. Conf. on Commun., Circuits and Syst. (ICCCAS). 871–875.

4. A new model for learning in graph domains

5. Will Hamilton, Zhitao Ying, and Jure Leskovec. 2017. Inductive representation learning on large graphs. Advances in Neural Information Process. Syst. 30 (2017).

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