An 8 GHz First-Order Frequency Synthesizer for Low-Power On-Chip Clock Generation
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/7166356/07106541.pdf?arnumber=7106541
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Design and Analysis of a Fractional Frequency Synthesizer With $<$90-fs Jitter and $<$ $-$103-dBc Spurious Tones Using Digital Spur Cancellation;IEEE Journal of Solid-State Circuits;2024
2. An integrated 0.0625–4 GHz quadrature-output fractional-N frequency synthesizer for software-defined radios;Microelectronics Journal;2022-01
3. A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications;International Journal of Circuit Theory and Applications;2019-08-04
4. A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH $\Delta \Sigma $ -TDC for Low In-Band Phase Noise;IEEE Journal of Solid-State Circuits;2017-07
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