1. Kehan Zhu, et.al.2015. "Design Analysis of a 12.5 GHz PLL in 130 nm SiGeBiCMOS Process," IEEE Workshop on Microelectronics and Electron Devices, pp 1--4, 2015.
2. Jin Yue, Hai Qi and Qiang Li,2012. "A 1GHz Charge Pump PLL Frequency Synthesizer for IEEE 1394b PHY," Journal of Electronic Science and Technology, vol, 10, no. 4, pp 319--326, Dec 2012.
3. F M Gardner,1980. "Charge-pump phase-lock loops," IEEE T COMMUN, vol-28, pp. 1849--58, Nov 1980.
4. R E Best, 2001. "Phase-Locked Loops: Design, Simulation, and Applications," Fourth Edition, McGraw Hill.
5. BehzadRazavi, 2001. "Design of Analog CMOS Integrated Circuits," McGraw Hill, 2001.