A 3-ns range, 8-ps resolution, timing generator LSI utilizing Si bipolar gate array
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx1/4/2580/00078252.pdf?arnumber=78252
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA;Applied Sciences;2019-07-03
2. An On-The-Fly Jitter Suppression Technique for Plain-CMOS-Logic-Based Timing Verniers: Dynamic Power Compensation with the Extensions of Digitally Variable Delay Lines;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2018-08-01
3. All-digital pulse-expansion-based CMOS digital-to-time converter;Review of Scientific Instruments;2017-02
4. Digital-to-Time Converter with 3.93 ps Resolution Implemented on FPGA Chips;IEEE Access;2017
5. A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance;SpringerPlus;2016-04-12
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