A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance-Reference-Cited by-同舟云学术

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A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance

Published:2016-04-12 Issue:1 Volume:5 Page:
ISSN:2193-1801
Container-title:SpringerPlus
language:en
Short-container-title:SpringerPlus

Author:

Abdulrazzaq Bilal I.,Abdul Halin Izhal,Kawahito Shoji,Sidek Roslina M.,Shafie Suhaidi,Yunus Nurul Amziah Md.

Funder

Universiti Putra Malayia (UPM)

Publisher

Springer Science and Business Media LLC

Subject

Multidisciplinary

Link

http://link.springer.com/content/pdf/10.1186/s40064-016-2090-z.pdf

Reference85 articles.

1. Abas MA, Russell G, Kinniment DJ (2007a) Built-in time measurement circuits—a comparative design study. Comput Digit Tech IET 1(2):87–97. doi: 10.1049/iet-cdt:20060111

2. Abas MA, Russell G, Kinniment DJ (2007b) Embedded high-resolution delay measurement system using time amplification. Comput Digit Tech IET 1(2):77–86. doi: 10.1049/iet-cdt:20060099

3. Adabi E, Niknejad AM (2008) Broadband variable passive delay elements based on an inductance multiplication technique. In: Radio frequency integrated circuits symposium (RFIC 2008). IEEE, June 17–April 17, pp 445–448. doi: 10.1109/rfic.2008.4561473

4. Akers LA (1980) The effect of field dependent mobility on the threshold voltage of a small geometry MOSFET. Solid State Electron 23(2):173–175. doi: 10.1016/0038-1101(80)90154-9

5. Alahmadi ANM (2013) Reconfigurable time interval measurement circuit incorporating a programmable gain time difference amplifier. Ph.D. dissertation, Newcastle University

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