An On-The-Fly Jitter Suppression Technique for Plain-CMOS-Logic-Based Timing Verniers: Dynamic Power Compensation with the Extensions of Digitally Variable Delay Lines-Reference-Cited by-同舟云学术

An On-The-Fly Jitter Suppression Technique for Plain-CMOS-Logic-Based Timing Verniers: Dynamic Power Compensation with the Extensions of Digitally Variable Delay Lines

Published:2018-08-01 Issue:8 Volume:E101.A Page:1185-1196
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

SHIBATA Nobutaro¹,NAKAMURA Mitsuo¹

Affiliation:

1. NTT Microsystem Integration Laboratories

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E101.A/8/E101.A_1185/_pdf

Reference18 articles.

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2. [2] N. Shibata, T. Ishihara, and J. Fujioka, “Performance estimation of synchronous fast SRAM macrocells: Test chip design and evaluation with LSI test systems,” IEICE Trans. Inf. & Syst. (Japanese Edition), vol.J79-D-I, no.12, pp.1171-1184, Dec. 1996.

3. [3] J. Moreira, “Development of an ATE test cell for at-speed characterization and production testing,” IEEE Intl. Test Conf. (ITC) Dig. Tech Papers, Paper 3.2, Nov. 2011. 10.1109/test.2011.6139134

4. [4] A.M. Majid and D.C. Keezer, “Multi-function multi-GHz ATE extension using state-of-the-art FPGAs,” IEEE Intl. Test Conf. (ITC) Dig. Tech Papers, Paper 11.4, Nov. 2011. 10.1109/test.2011.6139161

5. [5] D.C. Keezer, C.E. Gray, T.H. Chen, and A. Majid, “Practical methods for extending ATE to 40 and 50Gbps,” IEEE Intl. Test Conf. (ITC) Dig. Tech Papers, Lecture 2.1, Nov. 2013. 10.1109/test.2013.6651876